The design of a computer system may be broken down into three partsxe2x80x94system design, logic design, and circuit design. System design involves breaking the overall system into subsystems and specifying the characteristics of each subsystem. For example, system design of a computer system could involve specifying the number and type of memory units, arithmetic units, and input-output devices as well as the interconnection and control of these subsystems. Logic design involves determining how to interconnect basic logic building blocks to perform a specific function. An example of logic design is determining the interconnection of logic gates and flip-flops to perform binary addition. Circuit design involves specifying the interconnection of specific components such as resistors, diodes, and transistors to form logic building blocks.
One such logic building block is a flip-flop. A flip-flop is a memory element that that provides storage for at least one bit, i.e., it can at least store a xe2x80x981xe2x80x99 or a xe2x80x980.xe2x80x99 A type of flip-flop commonly used by high performance circuits is a static flip-flop (discussed below with reference to FIG. 1).
An important aspect of circuit design is how logic building blocks, such as flip-flops, are actually implemented in a computer system. A typical approach used to implement logic building blocks is through the use of complementary metal-oxide-semiconductor (xe2x80x9cCMOSxe2x80x9d) logic families. CMOS logic families use metal-oxide-semiconductor field-effect transistors (xe2x80x9cMOSFETsxe2x80x9d).
The use of MOSFET transistors is beneficial because lower currents are needed to operate these transistors than other types of devices. However, MOSFETs operate slower than devices used in other logic families. MOSFETs may be divided into two types of transistors: positive-channel metal-oxide semiconductor (xe2x80x9cPMOSxe2x80x9d) transistors and negative-channel metal-oxide semiconductor (xe2x80x9cNMOSxe2x80x9d) transistors. A transistor is xe2x80x98onxe2x80x99 when there is an electrical pathway across the transistor such that a voltage at one terminal of the transistor can be seen at another terminal of the transistor. NMOS transistors can be switched xe2x80x98onxe2x80x99 or xe2x80x98offxe2x80x99 by the movement of electrons, whereas PMOS transistors can be switched xe2x80x98onxe2x80x99 or xe2x80x98offxe2x80x99 by the movement of electron vacancies. Every MOSFET has a voltage threshold (xe2x80x9cVTxe2x80x9d) value, which is the voltage level at which the MOSFET switches xe2x80x98onxe2x80x99 or xe2x80x98off.xe2x80x99 Generally, an NMOS transistor switches xe2x80x98onxe2x80x99 when there is a high logic level applied to the input of the NMOS transistor and a PMOS transistor switches xe2x80x98onxe2x80x99 when there is a low logic level, e.g., ground, applied to the input of the PMOS transistor.
An implementation where the use of MOSFETs is exemplified involves a static flip-flop. FIG. 1 shows a circuit schematic of a typical conventional static flip-flop (10). The static flip-flop (10) includes a master stage (12) that drives a slave stage (14). Such static flip-flops are also known as xe2x80x9cmaster-slave static flip-flops.xe2x80x9d
The master stage (12) includes a first transmission gate (16) that is formed by a first PMOS transistor (18) and a first NMOS transistor (20), where the first PMOS transistor (18) and the first NMOS transistor (20) are in parallel. A data input, DATA, serves as an input to the master stage (12), and, in turn, serves as an input to the first transmission gate (16).
The first transmission gate (16) outputs to a first inverter (22), which, in turn, outputs to both the slave stage (14) and a second inverter (24). The second inverter (24) outputs back to the input of the first inverter (22). The configuration of the first and second inverters (22, 24) allows the value outputted to the slave stage (14) to be held constant when the first transmission gate (16) is switched xe2x80x98off,xe2x80x99 i.e., when data cannot pass through the first transmission gate (16).
The slave stage (14) includes a second transmission gate (26) formed by a second PMOS transistor (28) and a second NMOS transistor (30), where the second PMOS transistor (28) and the second NMOS transistor (30) are in parallel. The value outputted by the first inverter (22) in the master stage (12) serves as an input to the second transmission gate (26).
The second transmission gate (26) outputs to a third inverter (32), which, in turn, outputs to both an output, OUT, of the static flip-flop (10) and a fourth inverter (34). The fourth inverter (34) outputs back to the input of the third inverter (32). The configuration of the third and fourth inverters (32, 34) allows the value outputted to OUT to be held constant when the second transmission gate (26) is switched xe2x80x98off,xe2x80x99 i.e., when data cannot pass through the second transmission gate (26).
A clock signal, CLK, serves as an input to the first PMOS transistor (18), and an inverted clock signal, INV_CLK, serves as an input to the first NMOS transistor (20). Alternatively, CLK serves as an input to the second NMOS transistor (30), and INV_CLK serves as an input to the second PMOS transistor (28).
When CLK is at a low logic level (also referred to also as being xe2x80x9clowxe2x80x9d) and INV_CLK is accordingly at a high logic level (also referred to as being xe2x80x9chighxe2x80x9d), the first transmission gate (16) switches xe2x80x98on,xe2x80x99 i.e., conducts, because the first PMOS transistor (18) switches xe2x80x98onxe2x80x99 due to the low value of CLK at its input and because the first NMOS transistor (20) switches xe2x80x98onxe2x80x99 due to the high value of INV_CLK at its input. Because the first transmission gate (16) is switched xe2x80x98on,xe2x80x99 the value of DATA is able to pass through the first transmission gate (16) to the input of the first inverter (22), which, in turn, outputs the inverse of DATA to both the slave stage (14) and the second inverter (24).
Conversely, because CLK is low and INV_CLK is high, the second transmission gate (26) is switched xe2x80x98off,xe2x80x99 and, as a result, the value outputted from the first inverter (22) is not able to pass through the second transmission gate (26). However, because the second inverter (24) inputs the value outputted by the first inverter (22) and subsequently outputs back to the input of the first inverter (22), the value outputted from the first inverter (22) is held constant at the input of the second transmission gate (26).
When CLK goes high and INV_CLK accordingly goes low, the second transmission gate (26) switches xe2x80x98onxe2x80x99 because the second PMOS transistor (28) switches xe2x80x98onxe2x80x99 due to the low value of INV_CLK at its input and because the second NMOS transistor (30) switches xe2x80x98onxe2x80x99 due to the high value of CLK at its input. Because the second transmission gate (26) is now switched xe2x80x98on,xe2x80x99 the value outputted by the master stage (12) is able to pass through the second transmission gate (26) to the input of the third inverter (32), which, in turn, outputs the inverse of the value outputted by the master stage (12) to both OUT and the fourth inverter (34). Furthermore, because the fourth inverter (34) inputs the value outputted by the third inverter (32) and subsequently outputs back to the input of the third inverter (32), the value outputted from the third inverter (32) is held constant at OUT regardless of whether the second transmission gate (26) switches back xe2x80x98off.xe2x80x99 However, when the master stage (12) again drives the slave stage (14), OUT will change accordingly, i.e., the third and fourth inverters (32, 34) are strong enough to hold the value at OUT, but not strong enough to hold OUT when a value passes from the master stage (12) through the second transmission gate (26) to the input of the third inverter (32).
The static flip-flop (10) shown in FIG. 1 may be modified for testing purposes to include scan test capabilities. FIG. 2 shows a scan capable flip-flop (40) which can conduct both normal mode operations and scan mode operations. Normal mode operations include those operations dependent on actual input data, whereas scan mode operations include those operations dependent on a scan input value.
FIG. 2 includes a scan capable master stage (42) that includes a first transmission gate (44) and a second transmission gate (46). The first transmission gate (44) is formed by a first PMOS transistor (48) and a first NMOS transistor (50), where the first PMOS transistor (48) and the first NMOS transistor (50) are in parallel. A clock signal, CLK, serves as an input to the first PMOS transistor (48), and an inverted clock signal, INV_CLK, serves as an input to the first NMOS transistor (50). Moreover, a data input, DATA, serves as an input to the first transmission gate (44).
The second transmission gate (46) is formed by a second PMOS transistor (52) and a second NMOS transistor (54), where the second PMOS transistor (52) and the second PMOS transistor (54) are in parallel. A scan clock signal, SCLK, serves as an input to the second PMOS transistor (52), and an inverted scan clock signal, INV_SCLK, serves as an input to the second NMOS transistor (54). Moreover, a scan input signal, SI, serves as an input to the second transmission gate (46).
The output of the first transmission gate (44) and the output of the second transmission gate (46) serve as an input to a first inverter (56). The first inverter (56) outputs to both a slave stage (60) and a second inverter (58). The second inverter (58) outputs back to the input of the first inverter (56) to ensure that the value outputted to the slave stage (60) by the first inverter (56) is held constant while the first transmission gate (44) and/or the second transmission gate (46) switch xe2x80x98off.xe2x80x99 The slave stage (60) has the same configuration as that of the slave stage (14) in FIG. 1.
During normal mode operations, SCLK and INV_SCLK are disabled, or, in the alternative, are held constant such that the second transmission gate (46) is switched xe2x80x98off.xe2x80x99 Conversely, CLK and INV_CLK behave normally, and when CLK goes low and INV_CLK accordingly goes high, the first transmission gate (44) switches xe2x80x98onxe2x80x99 and allows the value of DATA to pass through the first transmission gate (44) to the input of the first inverter (56). Thereafter, the first inverter (56) outputs to the slave stage (60), which, in turn, will output the inverted value of the value outputted by the first inverter (56) to an output, OUT, of the scan capable flip-flop (40). However, recall that the slave stage (60) only switches xe2x80x98onxe2x80x99 when the first transmission gate (44) in the master stage (42) switches xe2x80x98off.xe2x80x99
During scan mode operations, CLK and INV_CLK are disabled, or, in the alternative, are held constant such that the first transmission gate (44) is switched xe2x80x98off.xe2x80x99 Conversely, SCLK and INV_SCLK behave normally, and when SCLK goes low and INV_SCLK accordingly goes high, the second transmission gate (46) switches xe2x80x98onxe2x80x99 and allows the value of SI to pass through the second transmission gate (46) to the input of the first inverter (56). Thereafter, the first inverter (56) outputs to the slave stage (60), which, in turn, will output the inverted value of the value outputted by the first inverter (56) to OUT. However, recall that the slave stage (60) only switches xe2x80x98onxe2x80x99 when the second transmission gate (46) in the master stage (40) switches xe2x80x98off.xe2x80x99
An alternative to the static flip-flop designs shown in FIGS. 1 and 2 is a flip-flop design that includes a dynamic input stage and a static output stage, and such a design is disclosed in U.S. Pat. No. 5,898,330 as a xe2x80x9cstatisized dynamic flip-flop.xe2x80x9d
FIG. 3 shows a block diagram of a statisized dynamic flip-flop (80). A dynamic input stage (82) is coupled to receive a data input, DATA, at a first input lead (84) of the dynamic input stage (82) and to receive a clock signal, CLK, at a second input lead (86) of the dynamic input stage (82). The dynamic input stage (82) outputs to an to output lead (88) an internal signal X. A static output stage (90) has a first input lead (92) connected to the output lead (88) of the dynamic input stage (82) through which the static output stage (90) receives the internal signal X. The static output stage (90) is coupled to receive CLK at a second input lead (94) of the static output stage (90). Further, the static output stage (90) outputs an output signal, OUT, at an output lead (96) of the static output stage (90). The statisized dynamic flip-flop (80) enters a precharge phase when CLK goes low and enters an evaluation phase when CLK goes high.
The statisized dynamic flip-flop (80) operates during the precharge phase as follows. The dynamic input stage (82) causes the internal signal X to be at a predetermined logic level, independent of the value at DATA. In other words, the dynamic input stage (82) causes the internal signal X to go high during the precharge phase regardless of the value at DATA. Conversely, the static output stage (90) maintains the value of OUT at the same value OUT had during the previous evaluation phase, independent of the value of the internal signal X.
The statisized dynamic flip-flop (80) operates during the evaluation phase as follows. The dynamic input stage (82) receives DATA and, in response, causes the internal signal X to have a value dependent on the value of DATA. Particularly, the dynamic input stage (82) causes the internal signal X to be the complement of DATA. As discussed above, before the start of the evaluation phase, the dynamic input stage (82) precharges the internal signal X to high. Then, depending upon the value of DATA at the start of the evaluation phase, the dynamic input stage (82) causes the internal signal X to go low or else remain high. When DATA is high at the initial portion of the evaluation phase, the dynamic input stage (82) causes the internal signal X to go low. Conversely, when DATA is low at the initial portion of the evaluation phase, the dynamic input stage (82) causes the internal signal to remain high.
In addition, the dynamic input stage (82) is implemented so that once the internal signal X goes low during the evaluation phase, the dynamic input stage (82) cannot again cause the internal signal X to have a high value during the same evaluation phase.
Further, a shutoff mechanism (not shown) in the dynamic input stage (82) maintains the value of the internal signal X at high, if the value of DATA does not change to a high value within a relatively short time period from the start of the evaluation phase. This relatively short time period gives the statisized dynamic flip-flop (80) an edge-triggered operation. Therefore, during the evaluation phase, the dynamic input stage (82) provides an internal signal X that either remains stable at a high value throughout the evaluation phase, or else goes from high to low shortly after the rising edge of CLK and remains low throughout the rest of the evaluation phase.
In addition, the transition to the evaluation phase causes the static output stage (90) to generate OUT having a value dependent on the value of the internal signal X from the dynamic input stage (82). Particularly, the static output stage (90) provides OUT having a value that is the complement of the value of the internal signal X. Because the value of the internal signal X remains stable throughout the evaluation phase shortly after the rising edge of CLK, the static output stage (90) provides OUT with a constant value throughout the rest of the clock cycle.
Through the use of the dynamic input stage (82), the setup time of the statisized dynamic flip-flop (80) is zero, i.e., DATA can arrive at the statisized dynamic flip-flop (80) at about the same time as the rising edge of CLK, thereby reducing the latency of the statisized dynamic flip-flop (80).
FIGS. 4a and 4b relate to a circuit schematic of a prior art embodiment of a scan capable statisized dynamic flip-flop. Particularly, FIG. 4a shows a header block (100) for the scan capable statisized dynamic flip-flop and FIG. 4b shows a core block (120) for the scan capable statisized dynamic flip-flop. The header block (100) drives the core block (120) by providing control signals that control the core block (120).
Referring to FIG. 4a, a scan enable signal, SE, which is an input to the header block (100), serves as a first input of a NAND gate (102). A clock signal, CLK, which is also an input to the header block (100), serves as an input to a first inverter (104). The first inverter (104) outputs to a second inverter (106), which, in turn, outputs to a third inverter (108), a fourth inverter (110), and an output, CK, of the header block (100). The third inverter (108) outputs to a second input of the NAND gate (102), which, in turn, outputs to another output, SE_CLK, of the header block (100). The fourth inverter (110) outputs to a fifth inverter (112), which, in turn, outputs to another output, DELAY_CK, of the header block (100). SE_CLK, DELAY_CK, and CK constitute control signals that are provided by the header block (100) to the core block (120) (shown in FIG. 4b).
During normal mode operations, i.e., xe2x80x9cscan is disabled,xe2x80x9d SE is low. Because SE is low, the NAND gate (102) outputs high on SE_CLK. This occurs because when an input to a NAND gate is low, the NAND gate outputs high regardless of the values at other inputs of the NAND gate. Further, during normal mode operations, when CLK is high, the second inverter (106) outputs high on CK (after a two stage delay due to the first inverter (104) and the second inverter (106)) and the fifth inverter (112) outputs low on DELAY_CK (after a four stage delay due to the first, second, fourth, and fifth inverters (104, 106, 110, 112)). Conversely, when CLK is low during normal mode operations, the second inverter (106) outputs low on CK (after a two stage delay due to the first inverter (104) and the second inverter (106)) and the fifth inverter (112) outputs low on DELAY_CK (after a four stage delay due to the first, second, fourth, and fifth inverters (104, 106, 110, 112)).
During scan mode operations, i.e., xe2x80x9cscan is enabled,xe2x80x9d SE is high. Because SE is high, the NAND gate (102) outputs the inverse of the value at its second input. This occurs because when one input to a two-input NAND gate is high, the NAND gate outputs the inverse of the value at its second input. When CLK goes high, the third inverter (108) outputs low (after a three stage delay due to the first, second, and third inverters (104, 106, 108)) to the second input of the NAND gate (102) causing the NAND gate (102) to output high on SE_CLK. Further, during scan mode operations, when CLK goes high, the second inverter (106) outputs high on CK (after a two stage delay due to the first inverter (104) and the second inverter (106)) and the fifth inverter (112) outputs high on DELAY_CK (after a four stage delay due to the first, second, fourth, and fifth inverters (104, 106, 110, 112)).
Conversely, when CLK goes low, the third inverter (108) outputs high (after a three stage delay due to the first, second, and third inverters (104, 106, 108)) to the second input of the NAND gate (102) causing the NAND gate (102) to output low on SE_CLK. Further, during scan mode operations, when CLK goes low, the second inverter (106) outputs low on CK (after a two stage delay due to the first inverter (104) and the second inverter (106)) and the fifth inverter (112) outputs low on DELAY_CK (after a four stage delay due to the first, second, fourth, and fifth inverters (104, 106, 110, 112)).
Referring now to FIG. 4b, the core block (120) of the scan capable statisized dynamic flip-flop inputs the control signals from the header block (100), along with inputting the scan enable signal, SE, a data input signal, DATA, and a scan input signal, SI.
DELAY_CK serves as an input to a first input of an AND gate (122), which, in turn, outputs to a first input of a first NOR gate (124). SE serves as a second input to the first NOR gate (124), which, in turn, outputs to a first NMOS transistor (126). DATA serves as an input to a second NMOS transistor (128) and CK serves as an input to a first PMOS transistor (130), a third NMOS transistor (132), and a fourth NMOS transistor (134). The first NMOS transistor (126) has a terminal connected to an internal node X (internal node X is a dynamic node and is synonymous with the xe2x80x9cinternal signal Xxe2x80x9d discussed above with reference to FIG. 3) and has another terminal connected to a terminal of the second NMOS transistor (128). The second NMOS transistor (128), in addition to having a terminal connected to a terminal of the first NMOS transistor (126), has another terminal connected to a terminal of the third NMOS transistor (132). The third NMOS transistor (132), in addition to having a terminal connected to a terminal of the second NMOS transistor (128), has another terminal connected to ground (136) (also referred to as xe2x80x9cconnected to lowxe2x80x9d).
The internal node X serves as an input to a second input of the AND gate (122), and is also connected to a terminal of the first PMOS transistor (130). The first PMOS transistor (130), in addition to having a terminal connected to the internal node X, has another terminal connected to a voltage source (138) (also referred to as xe2x80x9cconnected to highxe2x80x9d). Further, the internal node X serves as an input to a sixth inverter (140), a second PMOS transistor (142), and a fifth NMOS transistor (144). The sixth inverter (140) outputs to both an input of a third PMOS transistor (146) and an input of a sixth NMOS transistor (148). The third PMOS transistor (146) has a terminal connected to high (138) and has another terminal connected to the internal node X. The configuration of the sixth inverter (140) and the third PMOS transistor (146) is used to hold the internal node X when the internal node X is high.
The sixth NMOS transistor (148) has a terminal connected to the internal node X and has another terminal connected to the terminal of the third NMOS transistor (132) that is connected to the terminal of the second NMOS transistor (128). The second PMOS transistor (142) has a terminal connected to high (138) and has another terminal connected to both an input to a seventh inverter (150) and a terminal of the fourth NMOS transistor (134). The fourth NMOS transistor (134), in addition to having a terminal connected to both a terminal of the second PMOS transistor (142) and the input to the seventh inverter (150), has another terminal connected to a terminal of the fifth NMOS transistor (144). The fifth NMOS transistor (144), in addition to having a terminal connected to a terminal of the fourth NMOS transistor (134), has another terminal connected to ground (136).
The seventh inverter (150) outputs to both an output, OUT, of the scan capable statisized dynamic flip-flop and an eighth inverter (152). The eighth inverter (152) then outputs back to the input of the seventh inverter (150). The configuration of the seventh and eighth inverters (150, 152) ensures that OUT is held at a constant value when OUT is not being driven by either a connection to ground (136) through the fourth and fifth NMOS transistors (134, 144) or a connection to high (138) through the second PMOS transistor (142).
SE_CLK and SI serve as inputs to a second NOR gate (154). The second NOR gate (154) outputs to a seventh NMOS transistor (156). The seventh NMOS transistor (156) has a terminal connected to the internal node X and has another terminal connected to the terminal of the third NMOS transistor (132) that is connected to the terminal of the second NMOS transistor (128).
During normal mode operations, SE is low, and therefore, SE_CLK is high (discussed above with reference to FIG. 4a). Because SE_CLK is high, the second NOR gate (154) outputs low to the input of the seventh NMOS transistor (156) causing the seventh NMOS transistor (156) to switch or remain xe2x80x98off.xe2x80x99
The core block (120) of the scan capable statisized dynamic flip-flop enters the precharge phase when CK goes low. When CK goes low, the third NMOS transistor (132) switches xe2x80x98off,xe2x80x99 the fourth NMOS transistor (134) switches xe2x80x98off,xe2x80x99 and the first PMOS transistor (130) switches xe2x80x98on.xe2x80x99 Because the first PMOS transistor (130) switches xe2x80x98on,xe2x80x99 the internal node X gets connected to high (138) through the first PMOS transistor (130). Because the internal node X goes high, the fifth NMOS transistor (144) switches xe2x80x98onxe2x80x99 and the second PMOS transistor (142) remains or switches xe2x80x98off.xe2x80x99 Further, because the fourth NMOS transistor (134) and the second PMOS transistor (142) are switched xe2x80x98off,xe2x80x99 the value at OUT is held at the value it had during the previous evaluation phase.
At the start of the evaluation phase, that is, when CK goes high, the third NMOS transistor (132) switches xe2x80x98on,xe2x80x99 the fourth NMOS transistor (134) switches xe2x80x98on,xe2x80x99 and the first PMOS transistor (130) switches xe2x80x98off.xe2x80x99 If the value at DATA is high at the start of the evaluation phase, then the second NMOS transistor (128) switches xe2x80x98on.xe2x80x99 Before the rising edge of DELAY_CK arrives at the second input of the AND gate (122), the AND gate (122) outputs low to the first input of the first NOR gate (124), which, in turn, outputs high to the first NMOS transistor (126) causing the first NMOS transistor (126) to switch xe2x80x98on.xe2x80x99 Because the first, second, and third NMOS transistors (126, 128, 132) are now switched xe2x80x98on,xe2x80x99 the internal node X gets connected to low (136) through the first, second, and third NMOS transistors (126, 128, 132). When the internal node X goes low, the second PMOS transistor (142) switches xe2x80x98onxe2x80x99 causing the input to the seventh inverter (150) to go high due to it getting connected to high (138) through the second PMOS transistor (142). The seventh inverter (150) then outputs low on OUT.
Additionally, when the internal node X goes low, the sixth inverter (140) outputs high to the input of the sixth NMOS transistor (148) causing the sixth NMOS transistor (148) to switch xe2x80x98on.xe2x80x99 When the sixth NMOS transistor (148) switches xe2x80x98on,xe2x80x99 the internal node X also gets connected to low (136) through the sixth and third NMOS transistors (148, 132). Thus, only after a connection is established between ground (136) and the internal node X through the sixth and third NMOS transistors (148, 132), can DATA toggle back low. Else, if a connection between the internal node X and ground (136) through the sixth and third NMOS transistors (148, 132) is not established before DATA goes back low, then the internal node X loses any connection to ground (136) and the core block (120) behaves undesirably. Moreover, the amount of time that DATA must remain high after the start of the evaluation phase is referred to as xe2x80x9chold time.xe2x80x9d Furthermore, although the transition from the high value at DATA to the low value at OUT is relatively fast, the hold time for DATA is relatively long.
When DATA is low at the start of an evaluation phase, the second NMOS transistor (128) switches or remains xe2x80x98off.xe2x80x99 Because the second NMOS transistor (128) switches xe2x80x98off,xe2x80x99 the internal node X does not get connected to low (136) due to there being no connection to ground (136) through the first, second, and third NMOS transistors (126, 128, 132). Therefore, because the fourth NMOS transistor (134) was xe2x80x98onxe2x80x99 right when CK went high and because the fifth NMOS transistor (144) switches xe2x80x98onxe2x80x99 due to the internal node X being high at the start of the evaluation phase, the input to the seventh inverter (150) gets connected to low (136) through the fourth and fifth NMOS transistors (134, 144). Note that although the first PMOS transistor (130) switches xe2x80x98offxe2x80x99 due to CK going high at the start of the evaluation phase, the internal node X remains high due it being held high by the configuration of the sixth inverter (140) and the third PMOS transistor (146).
During scan mode operations, SE is high. Because SE is high, the first NOR gate (124) outputs low due to the fact that a NOR gate always outputs low when one of its inputs is high. Thus, because the first NOR gate (124) outputs low to the input of the first NMOS transistor (126), the first NMOS transistor (126) remains or switches xe2x80x98off.xe2x80x99
The core block (120) of the scan capable statisized dynamic flip-flop enters the precharge phase when CK goes low. When CK goes low, the third NMOS transistor (132) switches xe2x80x98off,xe2x80x99 the fourth NMOS transistor (134) switches xe2x80x98off,xe2x80x99 and the first PMOS transistor (130) switches xe2x80x98on.xe2x80x99 Because the first PMOS transistor (130) switches xe2x80x98on,xe2x80x99 the internal node X gets connected to high (138) through the first PMOS transistor (130). Because the internal node X goes high, the fifth NMOS transistor (144) switches xe2x80x98onxe2x80x99 and the second PMOS transistor (142) remains or switches xe2x80x98off.xe2x80x99 Further, because the fourth NMOS transistor (134) and the second PMOS transistor (142) are switched xe2x80x98off,xe2x80x99 the value at OUT is held constant at the value it had during the previous evaluation phase.
At the start of the evaluation phase, that is, when CK goes high, the third NMOS transistor (132) switches xe2x80x98on,xe2x80x99 the fourth NMOS transistor (134) switches xe2x80x98on,xe2x80x99 and the first PMOS transistor (130) switches xe2x80x98off.xe2x80x99 Also, as CK goes high, SE_CLK follows high after a two stage delay (due to the third inverter (108) and the NAND gate (102) shown in FIG. 4a). If the value at SI is high at the start of the evaluation phase (before the rising edge of SE_CLK arrives), then the second NOR gate (154) outputs low to the input of the seventh NMOS transistor (156) causing the seventh NMOS transistor (156) to switch or remain xe2x80x98off.xe2x80x99 Because the first PMOS transistor (130) switches xe2x80x98offxe2x80x99 due to CK going high and because the seventh NMOS transistor (156) switches xe2x80x98offxe2x80x99 due to SI being high and SE_CLK being low, the internal node X does not have either a connection to ground (136) through the seventh and third NMOS transistors (156, 132) or a connection to high (138) through the first PMOS transistor (130). Because the internal node X is not driven by a connection to ground (136) or high (138), the internal node X is held high by the configuration of the sixth inverter (140) and the third PMOS transistor (146). Further, because the internal node X remains high, the fifth NMOS transistor (144) remains xe2x80x98onxe2x80x99 and because the fourth NMOS transistor (134) is switched xe2x80x98onxe2x80x99 due to CK going high, the input to the seventh inverter (150) gets connected to low (136) through the fourth and fifth NMOS transistors (134, 144). The seventh inverter (150) then outputs high on OUT. Once the rising edge of SE_CLK arrives at the first input of the second NOR gate (154), the second NOR gate (154) continues to output low and the seventh NMOS transistor (156) remains switched xe2x80x98off.xe2x80x99
If the value at SI is low at the start of the evaluation phase (before the rising edge of SE_CLK), then the second NOR gate (154) outputs high to the input of the seventh NMOS transistor (156) causing the seventh NMOS transistor (156) to switch or remain xe2x80x98on.xe2x80x99 The second NOR gate (154) outputs high because both the value of SE_CLK at its first input and the value of SI at its second input are low. Because the seventh NMOS transistor (156) switches or remains xe2x80x98on,xe2x80x99 the internal node X goes low due to it getting connected to low (136) through the seventh and third NMOS transistors (156, 132) (recall that the third NMOS transistor (132) switches xe2x80x98onxe2x80x99 when CK goes high at the beginning of the evaluation phase).
When the internal node X goes low, the second PMOS transistor (142) switches xe2x80x98onxe2x80x99 causing the input to the seventh inverter (150) to get connected to high (138) through the second PMOS transistor (142). The seventh inverter (150) then outputs low on OUT.
Also, when the internal node X goes low, the sixth inverter (140) outputs high to the input of the sixth NMOS transistor (148) causing the sixth NMOS transistor (148) to switch xe2x80x98on.xe2x80x99 When the sixth NMOS transistor (148) switches xe2x80x98on,xe2x80x99 the internal node X gets connected to low (136) through the sixth and third NMOS transistors (148, 132). Thus, even after the rising edge of SE_CLK arrives and causes the seventh NMOS transistor (156) to switch xe2x80x98off,xe2x80x99 the internal node X remains low.
Further, the value at SI has to be held low until after the internal node X gets connected to low (136) through the sixth and third NMOS transistors (148, 132). This is necessary because if SI toggles back high before the internal node X gets connected to low (136) through the sixth and third NMOS transistors (148, 132), then the internal node X loses its connection to ground (136). Further, although the transition from the low value at SI to the low value at OUT is relatively fast, the hold time for SI is relatively long.
As mentioned above in the discussion with reference to FIG. 4b, one important consideration that needs to made in the design of a flip-flop, such as a statisized dynamic flip-flop, deals with the concept of hold time, i.e., the amount of time that data at an input of a circuit must be held after the start of an evaluation phase. In other words, hold time is the amount of time that data at an input must be held constant before it can change without affecting the state of the circuit. Another important concept deals with setup time, i.e., the amount of time that data at an input of a circuit must be present before the start of an evaluation phase. With reference to the scan capable statisized dynamic flip-flop discussed above with reference to FIGS. 4a and 4b, although the scan capable statisized dynamic flip-flop has virtually zero setup time, its hold time is relatively long. This is because although a value on the dynamic node of the statisized dynamic flip-flop is already established due to a data input at the start of an evaluation phase, the data input must be held after the start of the evaluation phase in order for the value on the dynamic node to remain established.
A prior art approach that has been used to reduce the hold time of a statisized dynamic flip-flop is exemplified by the block diagram shown in FIG. 5. FIG. 5 shows a dynamic input stage (160) and a static output stage (162). A clock signal, CLK, serves as an input to both the dynamic input stage (160) and the static output stage (162). In order to reduce the hold time of the statisized flip-flop, two inverters (164, 166) are introduced on a data input, DATA. The hold time is thus reduced by the amount of delay introduced by the inverters (164, 166). However, the setup time is increased by the same amount of delay that the hold time is reduced. Further, the amount of time necessary for DATA to trigger a change at the output, OUT, of the statisized dynamic flip-flop is also increased by the amount of delay that the hold time is reduced.
According to one aspect of the present invention, a flip-flop comprises a data setup node on which a first setup value resides during a precharge phase, a dynamic input stage that selectively establishes a value on a dynamic node at a start of an evaluation phase, a feedback stage that selectively establishes a value on the data setup node at the start of the evaluation phase, and a static output stage, where the first setup value is dependent on an input to the flip-flop, and where the value on the dynamic node selectively controls the static output stage.
According to another aspect, a method for performing low hold time operations using a flip-flop comprises inputting a first setup value onto a data setup node during a precharge phase, selectively establishing a value on a dynamic node at a start of an evaluation phase, and selectively establishing a value on the data setup node at the start of the evaluation phase, where the first setup value is dependent on an input to the flip-flop, and where the value established on the data setup node is dependent on the value on the dynamic node.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.